Programmingmodels for reconfigurable heterogeneous multi-cores

A paradigm shift from single-core to parallel multi-core processors has occurred over the last couple of years to further increase the performance of processors. Originating in high-performance computing, this trend has quickly reached general purpose and finally also embedded central processing units (CPUs). Continuing advances in chip manufacture will not only allow an increasing number of homogeneous CPU cores to be integrated in a single chip but will also allow for combining specialized cores to form a heterogeneous multi-core. Many experts believe that such heterogeneous multi-cores will provide advantages in performance and energy efficiency over homogeneous multi-cores, because the different cores can be tailored to specific applications.1 Although there are established methods for programming homogeneous multi-cores, the programming of heterogeneous multi-cores is still the subject of ongoing research. In our research, we are particularly interested in heterogeneous multi-cores that include both programmable instruction set processors as well as fixed and reconfigurable function hardware cores. Reconfigurable hardware cores leverage programmable hardware such as field programmable gate arrays. This technology permits the customization of hardware structures to implement highly specialized and efficient fixed-function coprocessors. This reconfiguration process is controlled by software and can occur either once at the startup of the system or even during runtime. Augmenting multi-core processors with reconfigurable cores is attractive, because the reconfigurability allows tailoring of the multi-core to particular applications after fabrication, and can thus be considered an enabling technology for building future self-aware adaptive computer systems. Programming such heterogeneous multi-cores with reconfigurable cores poses additional challenges. The main challenge Figure 1. Schematic view of a heterogeneous multi-core processor featuring central processing unit (CPU) cores and reconfigurable hardware cores controlled by the ReconOS reconfigurable operating system. sw: Software. hw: Hardware.